SN54AS286

具有总线驱动器奇偶校验 I/O 端口的 9 位奇偶校验发生器/校验器

The and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-driving

parity input/output I/O port for parity generation/checking. The word-length capability is easily expanded by cascading.

The transmit control input is implemented specifically to accommodate cascading. When is low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs A-I are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.

The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up or power down to prevent bus glitches.

The SN54AS286 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS286 is characterized for operation from 0°C to 70°C.

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Generate Either Odd or Even Parity forNine Data Lines

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Cascadable for n-Bit Parity

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Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port

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Glitch-Free Bus During Power Up/Down

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Package Options Include Plastic Small-Outline D Packages, Ceramic Chip Carriers FK, and Standard Plastic N and Ceramic J 300-mil DIPs