SN75LBC176A

差动总线收发器

The SN65LBC176A, SN65LBC176AQ, and differential bus transceivers are monolithic, integrated circuits designed for bidirectional data communication on multipoint bus-transmission lines. They are designed for balanced transmission lines and are compatible with ANSI standard A/EIA-485-A and ISO 8482. The A version offers improved switching performance over its predecessors without sacrificing significantly more power.

The SN65LBC176A, SN65LBC176AQ, and SN75LBC176A combine a 3-state, differential line driver and a differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can externally connect together to function as a direction control. The driver differential outputs and the receiver differential inputs connect internally to form a differential input/output I/O bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. This port features wide positive and negative common-mode voltage ranges, making the device suitable for party-line applications. Very low device supply current can be achieved by disabling the driver and the receiver.

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Designed for Signal Rates Up to 30 Mbps

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Bus-Pin ESD Protection Exceeds 12 kV HBM

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Compatible With ANSI Standard TIA/EIA-485-A and ISO 8482:1987E

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Low Skew

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Designed for Multipoint Transmission on Long Bus Lines in Noisy Environments

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Very Low Disabled Supply-Current Requirements...700 µA Maximum

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Common Mode Voltage Range of -7 V to 12 V

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Thermal-Shutdown Protection

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Driver Positive and Negative Current Limiting

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Open-Circuit Fail-Safe Receiver Design

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Receiver Input Sensitivity...±200 mV Max

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Receiver Input Hysteresis...50 mV Typ

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Glitch-Free Power-Up and Power-Down Protection

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Available in Q-Temp Automotive

High Reliability Automotive Applications

Configuration Control / Print Support

Qualification to Automotive Standards

LinBiCMOS and LinASIC are trademarks of Texas Instruments.

Signaling rate by TIA/EIA-485-A definition restrict transition times to 30% of the bit length, and much higher signaling rates may be achieved without this requirement as displayed in the _TYPICAL CHARACTERISTICS_ of this device.