SN74LVC1G125

具有三态输出的单路总线缓冲器闸

This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.

The device is a single line driver with a 3-state output. The output is disabled when the output-enable OE input is high.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G125 device is available in a variety of packages including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

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Available in the Ultra Small 0.64-mm2

Package DPW With 0.5-mm Pitch

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Supports 5-V VCC Operation

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Inputs Accept Voltages to 5.5 V

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Provides Down Translation to VCC

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Max tpd of 3.7 ns at 3.3 V

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Low Power Consumption, 10-μA Max ICC

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±24-mA Output Drive at 3.3 V

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Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection

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Latch-Up Performance Exceeds 100 mA

Per JESD 78, Class II

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ESD Protection Exceeds JESD 22

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2000-V Human-Body Model A114-A

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200-V Machine Model A115-A

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1000-V Charged-Device Model C101