S25FL064LABMFV010

闪存, 浮动门架构, 串行NOR, 64 Mbit, 8M x 8位, SPI, SOIC, 8 引脚

The Cypress FL-L Family devices are Flash Non-volatile Memory products using Floating Gate technology & 65-nm process lithography. The FL-L family connects to a host system via a Serial Peripheral Interface SPI. Traditional SPI single bit serial input and output Single I/O or SIO is supported as well as optional two bit Dual I/O or DIO and four bit wide Quad I/O QIO, and Quad Peripheral Interface QPI commands. In addition, there are Double Data Rate DDR read commands for QIO and QPI that transfer address and read data on both edges of the clock. The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4 KB sector, 32 KB half block sector, 64 KB block sector, or entire chip erase.

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100,000 Program-Erase Cycles, minimum

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20 Year Data Retention, minimum