多核固定和浮点系统级芯片 Multicore Fixed and Floating-Point System-on-Chip
* FourTMS320C66x DSP Core Subsystems at 1.00 GHz and1.2GHz * 153.6 GMAC/76.8 GFLOP @ 1.2GHz * 32KB L1P, 32KB L1D, 1024KB L2 Per Core * 2MB Shared L2 * Multicore Navigator and TeraNet Switch Fabric - 2 Tb * Network Coprocessors- Packet Accelerator, Security Accelerator * Four Lanes of SRIO 2.1 - 5 Gbaud Per Lane Full Duplex * Two Lanes PCIe Gen2 - 5 Gbaud Per Lane Full Duplex * HyperLink - 50Gbaud Operation, Full Duplex * Ethernet MAC Subsystem - Two SGMII Ports w/ 10/100/1000 Mbps operation * 64-Bit DDR3 Interface DDR3-1600 - 8 GByte Addressable Memory Space * Six Lane SerDes-Based Antenna Interface AIF2 -Operating at up to 6.144 Gbps * Hardware Coprocessors * -Enhanced Coprocessor for Turbo Encoding -Three Enhanced Coprocessors for Turbo Decoding -Four Viterbi Decoders -Three Fast Fourier Transform Coprocessors -Bit Rate CoProcessor -Two Receiver Accelerators for WCDMA -Transmitt Accelerator for WCDMA * Four Rake Search Accelerators for Chip Rate Processing and Reed-Muller Decoding * I2C Interface, 16 GPIO Pins, SPI Interface * Eight 64-Bit Timers, Three On-Chip PLLs
