TMS320DM8148CCYE1

数字信号处理器和控制器 - DSP, DSC DaVinci Dig Media Proc

* High-PerformanceDaVinci Video Processors * Up to 1-GHz ARM® Cortex®-A8 RISC Core * Up to 750-MHz C674x™ VLIW DSP * Up to 6000 MIPS and 4500 MFLOPS * Fully Software-Compatible with C67x+™, C64x+™ * ARM Cortex-A8Core * ARMv7 Architecture * In-Order, Dual-Issue, Superscalar Processor Core * Neon™ Multimedia Architecture * Supports Integer and Floating Point * Jazelle® RCT Execution Environment * ARM Cortex-A8 Memory Architecture * 32KB of Instruction and Data Caches * 512KB of L2 Cache * 64KB of RAM, 48KB of Boot ROM * TMS320C674xFloating-Point VLIW DSP * 64 General-Purpose Registers 32-Bit * Six ALU 32-/40-Bit Functional Units * Supports 32-Bit Integer, SP IEEE Single Precision/32-Bit and DP IEEE Double Precision/64-Bit Floating Point * Supports up to Four SP Adds Per Clock and Four DP Adds Every Two Clocks * Supports up to Two Floating-Point SP or DP Approximate Reciprocal or Square Root Operations Per Cycle * Two Multiply Functional Units * Mixed-Precision IEEE Floating-Point Multiply Supported up to: * 2 SP x SP → SP Per Clock * 2 SP x SP → DP Every TwoClocks * 2 SP x DP → DP Every Three Clocks * 2 DP x DP → DPEvery Four Clocks * Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-Bit Multiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle * C674xTwo-Level Memory Architecture * 32KB of L1P RAM/Cache With EDC * 32KB of L1D RAM/Cache * 256KB of L2 Unified Mapped RAM/Caches With ECC * System Memory Management UnitMMU * Maps C674x DSP and EDMA TC Memory Accesses to System Addresses * 128KBof On-Chip Memory Controller OCMC RAM * Imaging Subsystem ISS * Camera Sensor Connection * Parallel Connection for Raw up to 16-Bit and BT.656 or BT.1120 8- and 16-Bit * Image Sensor Interface ISIF for Handling Image and Video Data From the Camera Sensor * Resizer * Resizing Image and Video From 1/16x to 8x * Generating Two Different Resizing Outputs Concurrently * ProgrammableHigh-Definition Video Image Coprocessing HDVICP v2 Engine * Encode, Decode, Transcode Operations * H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, JPEG/MJPEG * Media Controller * Controls the HDVPSS, HDVICP2, and ISS * SGX530 3D Graphics Engine * Delivers up to 25 MPoly/sec * Universal Scalable Shader Engine * Direct3D Mobile, OpenGLES 1.1 and 2.0, OpenVG 1.0, OpenMax API Support * Advanced Geometry DMA Driven Operation * Programmable HQ Image Anti-Aliasing * Endianness * ARM and DSP Instructions/Data – Little Endian * HD VideoProcessing Subsystem HDVPSS * Two 165-MHz, 2-channel HD Video Capture Modules * One 16-/24-Bit Input or Dual 8-Bit SD Input Channels * One 8-/16-/24-Bit Input and One 8-Bit Only Input Channels * Two 165-MHz HD Video Display Outputs * One 16-, 24-, or 30-Bit Output and One 16- or 24-Bit Output * Composite or S-Video Analog Output * Macrovision® Support Available * Digital HDMI 1.3 Transmitter With Integrated PHY * Advanced Video Processing Features Such as Scan, Format, Rate Conversion * Three Graphics Layers and Compositors * Dual 32-BitDDR2/DDR3 SDRAM Interfaces * Supports up to DDR2-800 and DDR3-1066 * Up to Eight x 8 Devices Total 2GB of Total Address Space