TMS5702135DZWTQQ1

ARM Cortex-R4 180MHz 闪存：2MB RAM：256KB

* High-Performance Automotive-Grade Microcontroller forSafety-Critical Applications * Dual CPUs Running in Lockstep * ECC on Flash and RAM Interfaces * Built-In Self-Test BIST for CPU and On-chip RAMs * Error Signaling Module With Error Pin * Voltage and Clock Monitoring * ARMCortex-R4F 32-Bit RISC CPU * Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline * FPU With Single- and Double-Precision * 12-Region Memory Protection Unit MPU * Open Architecture With Third-Party Support * Operating Conditions * System Clock up to 180 MHz * Core Supply Voltage VCC: 1.2 V Nominal * I/O Supply Voltage VCCIO: 3.3 V Nominal * ADC Supply Voltage VCCAD: 3.0 to 5.25 V * Integrated Memory * 3MB of Program Flash With ECC LS3135 * 2MB of Program Flash With ECC LS2135/2125 * 256KB of RAM With ECC LS3135/2135 * 192KB of RAM With ECC LS2125 * 64KB of Flash With ECC for Emulated EEPROM * 16-Bit External MemoryInterface * Common PlatformArchitecture * Consistent Memory Map Across Family * Real-Time Interrupt R Timer OS Timer * 96-Channel Vectored Interrupt Module VIM * 2-Channel Cyclic Redundancy Checker CRC * Direct Memory Access DMAController * 16 Channels and 32 Control Packets * Parity Protection for Control Packet RAM * DMA Accesses Protected by Dedicated MPU * Frequency-Modulated Phase-Locked Loop FMPLLWith Built-In Slip Detector * Separate Nonmodulating PLL forFlexRay™ * Trace and CalibrationCapabilities * Embedded Trace Macrocell ETM-R4 * Data Modification Module DMM * RAM Trace Port RTP * Parameter Overlay Module POM * Multiple CommunicationInterfaces * FlexRay Controller With Two Channels * 8KB of Message RAM With Parity Protection * Dedicated Transfer Unit FTU * Three CAN Controllers DCANs * 64 Mailboxes, Each With Parity Protection * Compliant to CAN Protocol Version 2.0B * Standard Serial Communication Interface SCI * Local Interconnect Network LIN Interface Controller * Compliant to LIN Protocol Version 2.1 * Can be Configured as a Second SCI * Inter-Integrated Circuit I2C * Three Multibuffered Serial Peripheral Interfaces MibSPIs * 128 Words With Parity Protection Each * Two Standard Serial Peripheral Interfaces SPIs * Two NextGeneration High-End Timer N2HET Modules * N2HET1: 32 Programmable Channels * N2HET2: 18 Programmable Channels * 160-Word Instruction RAM Each With Parity Protection * Each N2HET Includes Hardware Angle Generator * Dedicated High-End Transfer Unit HTU With MPU for Each N2HET * Two 12-Bit Multibuffered ADCModules * ADC1: 24 Channels * ADC2: 16 Channels Shared With ADC1 * 64 Result Buffers With Parity Protection Each * General-Purpose Input/OutputGPIO Pins Capable of Generating Interrupts * Sixteen Pins on the ZWT Package * Four Pins on the PGE Package * IEEE1149.1 JTAG, Boundary Scan and ARM CoreSightComponents * JTAG Security Module * Packages * 144-Pin Quad Flatpack PGE [Green] * 337-Ball Grid Array ZWT [Green]