TPS3306-18DGK

TEXAS INSTRUMENTS  TPS3306-18DGK  电压监控器, 低电平有效, 漏极开路复位, 2监视器, 2.7V-6V输入, VSSOP-8

The is a dual-processor Supervisory Circuits with active-low open-drain output. It is designed for circuit initialization which requires two supply voltages, primarily in DSP and processor-based systems. The supervisory circuit is designed to monitor the nominal supply voltage. During power-on, /RESET is asserted when the supply voltage VDD becomes higher than 1.1V. Thereafter, the supervisory circuit monitors the SENSEn input and keeps /RESET active as long as SENSEn remains below the threshold voltage VIT. An internal timer delays the return of the /RESET output to the inactive state high to ensure proper system reset. The delay time, tdtyp=100ms, starts after SENSE1 and SENSE2 inputs have risen above the threshold voltage VIT. When the voltage at SENSE1 or SENSE2 input drops below the threshold voltage VIT, the output becomes active low again.

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Voltage monitor for power-fail or low-battery warning

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power-ON reset generator

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Open-drain reset and power-fail output

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Watchdog timer with 0.8 second time-out

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Defined /RESET output from VDD >= 1.1V

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15µA Typical supply current

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Green product and no Sb/Br