

高效预测同步降压驱动器
The is a high-speed synchronous buck drivers for todays high-efficiency, lower-output voltage designs. Using Predictive Gate Drive PGD control technology, these drivers reduce diode conduction and reverse recovery losses in the synchronous rectifier MOSFETs.
The UCC27223 includes an enable pin that controls the operation of both outputs. A logic latch is also included to keep both outputs low until the first PWM input pulse comes in. The RDSon of the SR pull-down sourcing device is also minimized for higher frequency operations.
This closed loop feedback system detects body-diode conduction, and adjusts deadtime delays to minimize the conduction time interval. This virtually eliminates body-diode conduction while adjusting for temperature, load- dependent delays, and for different MOSFETs. Precise gate timing at the nanosecond level reduces the reverse recovery time of the synchronous rectifier MOSFET body-diode, reducing reverse recovery losses seen in the main high-side MOSFET. The lower junction temperature in the low-side MOSFET increases product reliability. Since the power dissipation is minimized, a higher switching frequency can also be used, allowing for smaller component sizes.
The UCC27223 is offered in the thermally enhanced 14-pin PowerPAD package with 2°C/W jc.
Predictive Gate Drive and PowerPAD are trademarks of Texas Instruments Incorporated.