XC9572-15PQ100I

CPLD XC9500 Family 1.6K Gates 72 Macro Cells 55.6MHz 0.5um Technology 5V 100Pin PQFP

Description

The XC9572 is  a high-performance CPLD  providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of four 36V18 Function Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure2for the architecture overview.

Features

•  7.5 ns pin-to-pin logic delays on all pins

• fCNT to 125 MHz

•  72 macrocells with 1,600 usable gates

•  Up to 72 user I/O pins

•  5 V in-system programmable ISP

-  Endurance of 10,000 program/erase cycles

-  Program/erase over full commercial voltage and temperature range

•  Enhanced pin-locking architecture

•  Flexible 36V18 Function Block

-  90 product terms drive any or all of 18 macrocells within Function Block

-  Global and product term clocks, output enables, set and reset signals

•  Extensive IEEE Std 1149.1 boundary-scan JTAG support

•  Programmable power reduction mode in each macrocell

•  Slew rate control on individual outputs

•  User programmable ground pin capability

•  Extended pattern security features for design protection

•  High-drive 24 mA outputs

•  3.3 V or 5 V I/O capability

•  Advanced CMOS 5V FastFLASH technology

•  Supports parallel programming of more than one XC9500 concurrently

•  Available in 44-pin PLCC, 84-pin PLCC, 100-pin PQFP and 100-pin TQFP packages