XC2S30-5CSG144I

FPGA Spartan-II Family 30K Gates 972 Cells 263MHz 0.18um Technology 2.5V 144Pin CSBGA

Spartan®-II Field Programmable Gate Array FPGA IC 92 24576 972 144-TFBGA, CSPBGA

得捷:
IC FPGA 92 I/O 144CSBGA

安富利:
The Spartan-II family of FPGAs have a regular, flexible, programmable architecture of Configurable Logic Blocks CLBs, surrounded by a perimeter of programmable Input/Output Blocks IOBs. There are four Delay-Locked Loops DLLs, one at each corner of the die. Two columns of block RAM lie on opposite sides of the die, between the CLBs and the IOB columns. These functional elements are interconnected by a powerful hierarchy of versatile routing channels. Spartan-II FPGAs are customized by loading configuration data into internal static memory cells. Unlimited reprogramming cycles are possible with this approach. Stored values in these cells determine logic functions and interconnections implemented in the FPGA. Configuration data can be read from an external serial PROM master serial mode, or written into the FPGA in slave serial, slave parallel, or Boundary Scan modes. Spartan-II FPGAs are typically used in high-volume applications where the versatility of a fast programmable solution adds benefits. Spartan-II FPGAs are ideal for shortening product development cycles while offering a cost-effective solution for high volume production. Spartan-II FPGAs achieve high-performance, low-cost operation through advanced architecture and semiconductor technology. Spartan-II devices provide system clock rates up to 200 MHz. In addition to the conventional benefits of high-volume programmable logic solutions, Spartan-II FPGAs also offer on-chip synchronous single-port and dual-port RAM block and distributed form, DLL clock drivers, programmable set and reset on all flip-flops, fast carry logic, and many other features.

Chip1Stop:
FPGA Spartan?-II Family 30K Gates 972 Cells 263MHz 0.18um Technology 2.5V 144-Pin CSBGA