MC100EP52DR2G

MC100EP52 系列 730GHz 5.5 V ECL 差分 数据和时钟 D型双稳态触发器-SOIC-8

The MC10EP/100EP52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions pulled down to V the outputs of the device will remain stable.

Features

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330ps Typical Propagation Delay

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Maximum Frequency > 4 GHz Typical

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PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V

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NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V

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Open Input Default State

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Safety Clamp on Inputs

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Q Output will default LOW with inputs open or at VEE

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Pb-Free Packages are Available