RM48L530ZWTT

MCU 16Bit/32Bit RM48Lx30 ARM Cortex R4F RISC 2048KB Flash 1.2V/3.3V 337Pin NFBGA

* High-Performance Microcontroller for Safety-Critical Applications * Dual CPUs Running inLockstep * ECC on Flash and RAM Interfaces * Built-In Self-TestBIST for CPU and On-chip RAMs * Error Signaling Module With ErrorPin * Voltage and Clock Monitoring * ARM Cortex-R4F 32-Bit RISC CPU * Efficient 1.66DMIPS/MHz With 8-Stage Pipeline * FPU With Single- andDouble-Precision * 12-Region Memory Protection UnitMPU * Open Architecture With Third-Party Support * Operating Conditions * SystemClock up to 200 MHz * Core Supply Voltage VCC: 1.2 V Nominal * I/O SupplyVoltage VCCIO: 3.3 V Nominal * ADC Supply VoltageVCCAD: 3.0 to 5.25 V * Integrated Memory * 3MB ofProgram Flash With ECCRM48L930 * 2MBof Program Flash With ECCRM48L730/530 * 256KB of RAMWith ECCRM48L930/730 * 192KB of RAM With ECC RM48L530 * 64KB of Flash With ECC for EmulatedEEPROM * 16-Bit External Memory Interface * Common Platform Architecture * Consistent Memory Map AcrossFamily * Real-Time Interrupt R Timer OS Timer * 96-ChannelVectored Interrupt Module VIM * 2-Channel Cyclic Redundancy CheckerCRC * Direct Memory Access DMA Controller * 16 Channels and 32 Peripheral Requests * ParityProtection for Control Packet RAM * DMA Accesses Protected by DedicatedMPU * Frequency-Modulated Phase-Locked Loop FMPLL With Built-In SlipDetector * Separate Nonmodulating PLL * Trace and Calibration Capabilities * Embedded Trace Macrocell ETM-R4 * DataModification Module DMM * RAM Trace Port RTP * Parameter Overlay ModulePOM * Multiple Communication Interfaces * USB * 2-Port USB Host Controller * One Full-SpeedUSB Device Port * Three CAN ControllersDCANs * 64 Mailboxes, Each With ParityProtection * Compliant to CAN Protocol Version2.0B * Standard Serial Communication InterfaceSCI * Local Interconnect Network LIN InterfaceController * Compliant to LIN Protocol Version 2.1 * Can beConfigured as a Second SCI * Inter-Integrated CircuitI2C * Three Multibuffered Serial PeripheralInterfaces MibSPIs * 128 Words With Parity ProtectionEach * TwoStandard Serial Peripheral Interfaces SPIs * Two Next Generation High-End Timer N2HET Modules * N2HET1: 32 ProgrammableChannels * N2HET2: 18 Programmable Channels * 160-WordInstruction RAM Each With Parity Protection * Each N2HET Includes Hardware AngleGenerator * Dedicated High-End Transfer Unit HTU With MPU for Each N2HET * Two 12-Bit Multibuffered ADC Modules * ADC1: 24 Channels * ADC2: 16 Channels Shared WithADC1 * 64 Result Buffers With Parity Protection Each * General-Purpose Input/Output GPIO Pins Capable of GeneratingInterrupts * 16 Pins on the ZWT Package * 10 Pins on the PGEPackage * IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components * JTAG Security Module * Packages * 144-PinQuad Flatpack PGE [Green] * 337-BallGrid Array ZWT [Green]