CD4076BE

TEXAS INSTRUMENTS  CD4076BE  移位寄存器, D型, 1元件, DIP, 16 引脚, 3 V, 18 V

The is a 4-bit CMOS D-type Register with clock and 3-state outputs. Data disable inputs are provided to control the entry of data into the flip-flops. When both data disable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the clock input. Output disable inputs are also provided. When the output disable inputs are both low, the normal logic states of the four outputs are available to the load. The outputs are disabled independently of the clock by a high logic level at either output disable input and present a high impedance.

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Three-state outputs

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Input disabled without gating the clock

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Gated output control lines for enabling or disabling the outputs

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Standardized, symmetrical output characteristics

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100% Tested for quiescent current at 20V

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Maximum input current of 1µA at 18V

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±10mA DC input current