M100LVEP111FATWG

MC100LVEP111: 2.5 V / 3.3 V 2:1:10 差分 ECL/PECL/HSTL 时钟/数据扇出缓冲器

The MC100LVEP111 is a low skew 2:1:10 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or single-ended if the V output is used. HSTL inputs can be used when the LVEP111 is operating under PECL conditions.The LVEP111 specifically guarantees low output-to-output skew.Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure tightest skew, both sides of differential outputs identically terminate into 50 ohms even if only one side is being used. When fewer than all ten pairs are used, identically terminate all the output pairs on the same package side whether used or unused. If no outputs on a single side are used, then leave these outputs open unterminated. This will maintain minimum output skew. Failure to do this will result in a 10-20 ps loss of skew margin propagation delay in the outputs in use.

Features

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85 ps Typical Device-to-Device Skew

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20 ps Typical Output-to-Output Skew

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Jitter Less than 1 ps RMS

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Additive RMS Phase Jitter: 60fs @156.25MHz, Typical

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Maximum Frequency >3 Ghz Typical

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VBB Output

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430 ps Typical Propagation Delay

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The 100 Series Contains Temperature Compensation

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PECL and HSTL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V

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NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V

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Open Input Default State

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LVDS Input Compatible