SN74AVC16334DGGR

具有三态输出的 16 位通用总线驱动器 48-TSSOP -40 to 85

description

A Dynamic Output Control DOC circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOLvs IOLand VOHvs IOHcurves to illustrate the output impedance and drive capability of the circuit.

Member of the Texas Instruments WidebusFamily

EPICEnhanced-Performance Implanted CMOS Submicron Process

DOCDynamic Output Control Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation

Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC

Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications

Ioff Supports Partial-Power-Down Mode Operation

Ideal for Use in PC133 Registered DIMM Applications

ESD Protection Exceeds JESD 22

  – 2000-V Human-Body Model A114-A

  – 200-V Machine Model A115-A

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Package Options Include Plastic Thin

  Shrink Small-Outline DGG and Thin Very

  Small-Outline DGV Packages