SN74AUP1G34

低功耗单缓冲器闸

This single buffer gate performs the Boolean function Y = A in positive logic.

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Available in the Ultra Small 0.64 mm2 Package DPW with 0.5-mm Pitch

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Low Static-Power Consumption;

ICC = 0.9 μA Max

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Low Dynamic-Power Consumption;

Cpd = 4.1 pF Typ at 3.3 V

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Low Input Capacitance; Ci = 1.5 pF Typ

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Low Noise - Overshoot and Undershoot < 10% of VCC

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Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection

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Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input

Vhys = 250 mV Typ at 3.3 V

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Wide Operating VCC Range of 0.8 V to 3.6 V

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Optimized for 3.3-V Operation

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3.6-V I/O Tolerant to Support Mixed-Mode

Signal Operation

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tpd = 4.1 ns Max at 3.3 V

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Suitable for Point-to-Point Applications

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Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

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ESD Performance Tested Per JESD 22

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2000-V Human-Body Model

A114-B, Class II

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1000-V Charged-Device Model C101