74HC373D

NXP  74HC373D  逻辑芯片, CMOS, SMD, 74HC373, SOIC20

The is an octal transparent D Latch with 3-state outputs. It features LE and OE\ inputs. When LE is high, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is low the latches store the information that was present at the inputs a set-up time preceding the high-to-low transition of LE. A high on OE\ causes the outputs to assume a high-impedance OFF-state. Operation of the OE\ input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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3-state Non-inverting outputs for bus oriented applications

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Common 3-state output enable input

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CMOS Input level

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TTL Input level

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Complies with JEDEC standard No. 7A