74HC377D

NXP  74HC377D  触发器, 数据许可, 非反相, 正沿, D, 13 ns, 77 MHz, 7.8 mA, SOIC, 20 引脚

The is an Octal D-type Flip-flop with data enable and positive-edge trigger. It features clock and data enable E\\ inputs. When E is low, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the low-to-high clock transition. Input E\ must be stable one set-up time prior to the low-to-high transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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Common clock and master reset

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Eight positive edge-triggered D-type flip-flops

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CMOS Input levels

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Complies with JEDEC standard No. 7A