74HC75D

NXP  74HC75D  芯片, 74HC CMOS逻辑器件

The is a quad bistable Transparent Latch with complementary outputs. Two latches are simultaneously controlled by one of two active high enable inputs LE12 and LE34. When LEnn is high, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs nD as long as LEnn is high transparent. The data on the nD inputs one set-up time prior to the high-to-low transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is low. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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Complementary Q and Q\ outputs

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VCC and GND on the center pins

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Low-power dissipation

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CMOS Input level

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Complies with JEDEC standard No. 7A