74系列逻辑芯片/74AHC573D
DESCRIPTION
The 74AHC/AHCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL LSTTL. They are specified in compliance with JEDEC standard No. 7A.
The 74AHC/AHCT573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A Latch Enable LE input and an Output Enable OE input are common to all latches.
FEATURES
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Common 3-state output enable input
• Functionally identical to the ‘563" and ‘373’
• Inputs accepts voltages higher than VCC
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 and +125°C.