八路D - FL型IP- FL操作;正边沿触发;三态 Octal D-type flip-flop; positive edge-trigger; 3-state
General description
The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL LSTTL. They are specified in compliance with JEDEC standard no. 7A.
The 74AHC574; 74AHCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock CP and an output enable OE input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition.
Features
■ Balanced propagation delays
■ All inputs have a Schmitt-trigger action
■ 3-state non-inverting outputs for bus orientated applications
■ 8-bit positive, edge-triggered register
■ Independent register and 3-state buffer operation
■ Common 3-state output enable input
■ For 74AHC574 only: operates with CMOS input levels
■ For 74AHCT574 only: operates with TTL input levels
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C