74VHC138MTC

FAIRCHILD SEMICONDUCTOR  74VHC138MTC  芯片, 解码器/信号分离器, 3:8, TSSOP-16

The is an advanced high speed CMOS 3-to-8 Decoder/Demultiplexer fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. When the device is enabled, 3 binary select inputs A0, A1 and A2 determine which one of the outputs O#0-O#7 will go LOW. When enable input E3 is held LOW or either E#1 or E#2 is held HIGH, decoding function is inhibited and all outputs go HIGH. E3, E#1 and E#2 inputs are provided to ease cascade connection and for use as an address decoder for memory systems. An input protection circuit ensures that 0 to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.

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5.7ns typical at 25°C High speed

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4µA maximum at 25°C Low power dissipation

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28% VCC minimum High noise immunity

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Power down protection provided on all inputs