74LVC573APW,118

NXP  74LVC573APW,118  芯片, 锁存器, D型, 透明, 三态, TSSOP-20

The 74LVC573APW is an octal transparent D Latch with 5V tolerant inputs/outputs. It features separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enables input pin LE and an output enable input pin OE\\ is common to all internal latches. When pin LE is high, data at the D-inputs pins D0 to D7 enters the latches. In this condition, the latch is transparent, that is, a latch output will change each time its corresponding D-input changes. When pin LE is low, the latch stores the information that was present at the D-inputs one set-up time preceding the high-to-low transition of pin LE. When pin OE\ is low, the contents of the eight latches are available at the Q-outputs pins Q0 to Q7. When pin OE\ is high, the outputs go to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latches. Inputs can be driven from either 3.3 or 5V devices.

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CMOS low power consumption

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Direct interface with TTL levels