74LVC574APW,118

NXP  74LVC574APW,118  触发器, 三态, 正沿, D, 200 MHz, TSSOP, 20 引脚

The 74LVC574APW is an octal positive-edge triggered D-type Flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A clock and an OE\ input are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the low to high CP transition. When OE\ is low, the contents of the eight flip-flops are available at the outputs. When OE\ is high, the outputs go to the high-impedance OFF-state. Operation of the OE\ input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 or 5V devices. When disabled, up to 5.5V can be applied to the outputs. These features allow the use of this device as translators in mixed 3.3 or 5V applications. The 74LVC574A is functionally identical to the 74LVC374A, but has a different pin arrangement.

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CMOS low power consumption

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Direct interface with TTL levels

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Flow-through pin-out architecture

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High-impedance when VCC = 0V