74LVC138APW,118

NXP  74LVC138APW,118  芯片, 解码器/信号分离器, 3:8, TSSOP-16

The 74LVC138APW is a 3-to-8 Decoder/Demultiplexer accepts three binary weighted address inputs A0, A1 and A2 and, when enabled, provides eight mutually exclusive outputs Y0\ to Y7\\ that are low when selected. There are three enable inputs: two active low E1\ and E2\\ and one active high E3. Every output will be high unless E1\ and E2\ are low and E3 is high. This multiple enable function allows easy parallel expansion of the device to a 1-of-32 5 lines to 32 lines decoder with just four 74LVC138A devices and one inverter. The 74LVC138A can be used as an eight output demultiplexer by using one of the active low enable inputs as the data input and the remaining enable inputs as strobes. Unused enable inputs must be permanently tied to their appropriate active high or low state.

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CMOS low power consumption

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Direct interface with TTL levels

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Demultiplexing capability

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Multiple input enable for easy expansion

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Ideal for memory chip select decoding

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Mutually exclusive outputs

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Output drive capability 50R transmission lines at 125°C