74HCT652D,118

NXP 74HCT652D,118 Transceiver, Non-Inverting, 4.5V to 5.5V, SOIC-24

The is an octal non-inverting bus transceiver/register with 3-state outputs, D-type flip-flops and central circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the A or B or both buses, will be stored in the internal registers, at the appropriate clock pins regardless of the select pins or output enable control pins. Depending on the select inputs SAB and SBA data can directly go from input to output or data can be controlled by the clock, this when the output enable pins this operating mode permits. The output enable pins OEAB and OEBA determine the operation mode of the transceiver. When OEAB is LOW, no data transmission from An to Bn is possible and when OEBA is HIGH, there is no data transmission from Bn to An possible. When SAB and SBA are in the real time transfer mode, it also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA.

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Low-voltage Si-gate CMOS

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Multiplexed real-time and stored data

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Independent register for A and B buses

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Independent enables for A and B buses

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Output capability - Bus driver

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Low power consumption by CMOS technology

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Schmitt-trigger action in clock inputs makes circuit highly tolerant to slower clock rise/fall times

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Pin compatible with low power Schottky TTL

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ICC category - MSI

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Compliance with Jedec standard no. 7A