74HC4052PW-Q100,11

NXP  74HC4052PW-Q100,11  芯片, 模拟多路复用器/信号分离器, 双路, 4X1, TSSOP-16

The 74HC4052PW-Q100 is a dual 4-channel Analog Multiplexer/Demultiplexer with common select logic. It is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL LSTTL. Each multiplexer has four independent inputs/outputs pins nY0 to nY3 and a common input/output pin nZ. The common channel select logics include two digital select inputs pins S0 and S1 and an active LOW enable input pin E. VCC and GND are the supply voltage pins for the digital control inputs pins S0, S1 and E. The analog inputs/outputs pins nY0 to nY3 and nZ can swing VEE may not exceed between VCC as a positive limit and VEE as a negative limit. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND typically ground.

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Low ON resistance - 80R, 70R, 60R typical at VCC-VEE = 4.5V, 6.0V, 9.0V respectively

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Logic level translation to enable 5V logic to communicate with ±5V analog signals

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Typical break before make built-in

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ESD protection - MIL-STD-833, method 3015 <2000V, HBM JESD22-A114F <2000V, MM JESD22-A115-A <200V