74HC193PW,118

NXP  74HC193PW,118  芯片, 二进制计数器, 向上/向下, 49MHZ, TSSOP-16

The 74HC193PW is a 4-bit presettable synchronous Binary Up/Down Counter with separate up/down clocks, CPU and CPD respectively. The outputs change state synchronously with the low-to-high transition of either clock input. If the CPU clock is pulsed while CPD is held high, the device will count up. If the CPD clock is pulsed while CPU is held high, the device will count down. Only one clock input can be held high at any time to guarantee predictable behaviour. The device can be cleared at any time by the asynchronous master reset input MR, it may also be loaded in parallel by activating the asynchronous parallel load input PL\\. The terminal count up TCU\\ and terminal count down TCD\\ outputs are normally high. When the circuit has reached the maximum count state of 15, the next high-to-low transition of CPU will cause TCU\ to go low. TCU\ will stay low until CPU goes high again, duplicating the count up clock.

.

Asynchronous parallel load

.

Asynchronous reset

.

Expandable without external logic

.

CMOS Input levels

.

Complies with JEDEC standard No. 7A