74HCT373N

NXP  74HCT373N  芯片, 74HCT CMOS逻辑器件

The is a 3-state octal D-type Transparent Latch with high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL. It is specified in compliance with JEDEC standard no-7A. It features separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable LE input and an output enable OE input are common to all latches. The latch consists of eight D-type transparent latches with 3-state true outputs. When LE is high, data at the Dn inputs enters the latches. In this condition the latches are transparent, that is a latch output will change state each time its corresponding D input changes.

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Common 3-state output enable input

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ESD protection HBM JESD22-A114F exceeds 2000V

ESD sensitive device, take proper precaution while handling the device.