74AHC573PW,118

NXP  74AHC573PW,118  芯片, 锁存器, D型, 透明, 三态, TSSOP-20

The 74AHC573PW is an octal transparent D Latch pin compatible with low-power Schottky TTL LSTTL. It consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications. A LE and an OE are common to all latches. When pin LE is high, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding Dn input changes. When pin LE is low, the latches store the information that is present at the Dn inputs, after a set-up time preceding the high-to-low transition of LE. When pin OE is low, the contents of the 8 latches are available at the outputs. When pin OE is high, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches.

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Balanced propagation delays

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All inputs have a Schmitt trigger action

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Common 3-state output enable input

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Inputs accept voltages higher than VCC

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CMOS Input level

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Complies with JEDEC standard No. 7A