74HC259D

NXP  74HC259D  芯片, 74HC CMOS逻辑器件

The is a 8-bit Addressable Latch features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs AO to A3. The addressed latch will follow the data input, non-addressed latches will retain their previous states. In memory mode, all latches retain their previous states and are unaffected by the data or address inputs. In the 3-to-8 decoding or demultiplexing mode, the addressed output follows the D input and all other outputs are low. In the reset mode, all outputs are forced low and unaffected by the data or address inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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Serial-to-parallel capability

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Output from each storage bit available

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Random addressable data entry

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Easily expandable

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Common reset input

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Useful as a 3-to-8 active high decoder

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CMOS Input level

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Complies with JEDEC standard No. 7A