74HC138D

NXP  74HC138D  芯片, 74HC CMOS逻辑器件

The is a high speed Si-gate CMOS device and is pin compatible with low power Schottky TTL LSTTL. The 74HC138D decoder accepts three binary weighted address inputs A0, A1 and A3 and when enabled, provides 8 mutually exclusive active LOW outputs Y0 to Y7. This device features three enable inputs: two active LOW E1 and E2 and one active HIGH E3. Every output is HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 5 lines to 32 lines decoder with just four 74HC138D ICs and one inverter. This device can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Permanently tie unused enable inputs to their appropriate active HIGH- or LOW-state.

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Demultiplexing capability

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Multiple input enable for easy expansion

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Complies with JEDEC standard no. 7A

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Ideal for memory chip select decoding

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Active LOW mutually exclusive outputs

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HBM EIA/JESD22-A114-F exceeds 2000V

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MM EIA/JESD22-A115-A exceeds 200V