74LVC2G74GF

NXP  74LVC2G74GF  触发器, 差分, 正沿, D, 2.5 ns, 200 MHz, 50 mA, XSON, 8 引脚

The is a single positive-edge triggered D-type Flip-flop with individual data D inputs, clock inputs, set S\D and reset R\D inputs and complementary Q and Q\ outputs. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active low inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the low-to-high transition of the clock pulse. The D inputs must be stable, one set-up time prior to the low-to-high clock transition for predictable operation. Schmitt-trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

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High noise immunity

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CMOS low power consumption

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Latch-up performance exceeds 250mA

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Direct interface with TTL levels

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±24mA Output drive current