74LV74PW,118

NXP  74LV74PW,118  触发器, 互补输出, 正沿, D, 100 MHz, 25 mA, TSSOP, 14 引脚

The 74LV74PW is a dual positive-edge trigger D-type Flip-flop with set and reset. It has individual data nD inputs, clock nCP inputs, set nSD\\ and nRD\\ inputs and complementary nQ and nQ\ outputs. The set and reset are asynchronous active low inputs that operate independently of the clock input. Information on the data input is transferred to the nQ output on the low-to-high transition of the clock pulse. The nD inputs must be stable one set-up time prior to the low-to-high clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

.

Direct interface with TTL levels

.

Optimized for low voltage applications