74HCT175D,652

NXP  74HCT175D,652  触发器, 互补输出, 正沿, D, 54 MHz, 25 mA, SOIC, 16 引脚

The 74HCT175D is a quad positive-edge triggered D-type Flip-flop with individual data inputs Dn and complementary outputs Qn and Qn\\. The common clock and master reset MR\\ inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the low-to-high clock transition will be stored in the flip-flop and appear at the Q output. A low on MR\ causes the flip-flops and outputs to be reset low. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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Asynchronous master reset

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Complies with JEDEC standard no. 7A

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TTL Input levels