74HC4024D

NXP  74HC4024D  芯片, 逻辑电路 - 74HC, 计数器, SO14

The is a 7-stage Binary Ripple Counter with a clock input CP\\, an overriding asynchronous master reset input MR and seven fully buffered parallel outputs Q0 to Q6. The counter advances on the high-to-low transition of CP\\. A high on MR clears all counter stages and forces all outputs low, independent of the state of CP\\. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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Low-power dissipation

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CMOS Input levels

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Complies with JEDEC standard No. 7A