74HCT165N

NXP  74HCT165N  移位寄存器, 并行至串行, 1元件, DIP, 16 引脚, 4.5 V, 5.5 V

The is a 8-bit serial or parallel-in/serial-out Shift Register features a serial data input DS, eight parallel data inputs D0 to D7 and two complementary serial outputs Q7 and Q7\\. When the parallel load input PL\\ is low the data from D0 to D7 is loaded into the shift register asynchronously. When PL\ is high data enters the register serially at DS. When the clock enable input CE\\ is low data is shifted on the low-to-high transitions of the CP input. A high on CE\ will disable the CP input. Inputs include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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Asynchronous 8-bit parallel load

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Synchronous serial input

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TTL Input level

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Complies with JEDEC standard No. 7A