74HC4040N

NXP  74HC4040N  芯片, 74HC CMOS逻辑器件

The is a 12-stage Binary Ripple Counter with a clock input CP\\, an overriding asynchronous master reset input MR and twelve parallel outputs Q0 to Q11. The counter advances on the high-to-low transition of CP\\. A high on MR clears all counter stages and forces all outputs low, independent of the state of CP\\. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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CMOS Input levels

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Complies with JEDEC standard No. 7A