NXP 74LVT573PW,118 芯片, 锁存器, D型, 透明, 三态, TSSOP-20
The 74LVT573PW is an octal BiCMOS transparent D Latch designed for VCC operation at 3.3V. It is coupled to eight 3-state output buffers. The two sections of the device are controlled independently by LE and OE\ control gates. It has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the Dn inputs are transferred to the latch outputs when the LE input is high. The latch remains transparent to the data inputs while LE is high and stores the data that is present one setup time before the high-to-low enable transition. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories or MOS microprocessors. The active-low OE\ controls all eight 3-state buffers independent of the latch operation. When OE\ is low, the latched or transparent data appears at the outputs.
电源电压DC 2.70V min
输出接口数 8
针脚数 20
位数 8
输入数 8
工作温度Max 85 ℃
工作温度Min -40 ℃
电源电压 2.7V ~ 3.6V
电源电压Max 3.6 V
电源电压Min 2.7 V
安装方式 Surface Mount
引脚数 20
封装 TSSOP-20
高度 0.95 mm
封装 TSSOP-20
工作温度 -40℃ ~ 85℃
产品生命周期 Active
包装方式 Tape & Reel TR
制造应用 Computers & Computer Peripherals, Communications & Networking
RoHS标准 RoHS Compliant
含铅标准 Lead Free
REACH SVHC标准 No SVHC
REACH SVHC版本 2015/12/17