74HCT109PW

NXP  74HCT109PW  触发器, 互补输出, 正沿, JK, 20 ns, 61 MHz, 4 mA, TSSOP, 16 引脚

The is a positive-edge trigger Dual J K\ Flip-flop with set and reset. This high-speed Si-gate CMOS device is pin compatible with low power Schottky TTL LSTTL. It is specified in compliance with JEDEC standard no. 7A. The dual positive-edge triggered J K\ flip-flops with individual J, K\ inputs, clock CP inputs, set SD\\ and reset RD\\ inputs, also complementary Q and Q\ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K\ inputs control the state changes of the flip-flops as described in the mode select function table. The J and K\ inputs must be stable one set-up time prior to the low-to-high clock transition for predictable operation. The J K\ design allows operation as a D-type flip-flop by tying the J and K\ inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

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J, K\ Inputs for easy D-type flip-flop

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Toggle flip-flop

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Standard output capability

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ICC Category