74LV573PW,112

NXP  74LV573PW,112  芯片, 锁存器, D型, 透明, 三态, TSSOP-20

The 74LV573PW is an octal CMOS transparent D Latch features separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A LE input and an OE\ input are common to all internal latches. When LE is high, data at the Dn inputs enters the latches. In this condition, the latch is transparent, that is, a latch output will change each time its corresponding D-input changes. When LE is low, the latches store the information that was present at the D-inputs one set-up time preceding the high-to-low transition of LE. When OE\ is low, the contents of the eight latches are available at the outputs. When OE\ is high, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The 74LV573 is functionally identical to the 74LV373, but has a different pin arrangement.

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Inputs and outputs on opposite sides of package allowing easy interface with microprocessors

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Useful as input or output port for microprocessors

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Common 3-state output enable input

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Optimized for low voltage applications

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Accepts TTL input levels between 2.7 and 3.6V VCC