SRAM Chip Sync Single 3.3V 4.5M-Bit 256K x 18 4.2ns 100Pin TQFP
* 128K x 36, 256K x 18 memory configurations * Supports high performance system speed - 200 MHz x18 3.2 ns Clock-to-Data Access * Supports high performance system speed - 166 MHz x36 3.5 ns Clock-to-Data Access * ZBTTM Feature - No dead cycles between write and read cycles * Single R/W READ/WRITE control pin * Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications * 4-word burst capability interleaved or linear * Three chip enables for simple depth expansion * 3.3V power supply ±5%, 3.3V I/O Supply VDDQ * Optional- Boundary Scan JTAG Interface IEEE 1149.1 compliant * Packaged in a JEDEC standard 100-pin plastic thin quad flatpack TQFP, 119 ball grid array BGA and 165 fine pitch ball grid array fBGA