六路D - FL型IP- FL运带复位;正边沿触发 Hex D-type flip-flop with reset; positive-edge trigger
General description
The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs Dn and outputs Qn. The common clock CP and master reset MR inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Features and benefits
Input levels:
For 74HC174: CMOS level
For 74HCT174: TTL level
Six edge-triggered D-type flip-flops
Asynchronous master reset
Complies with JEDEC standard no. 7A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Specified from -40℃ to +85℃ and from -40℃ to +125℃