时钟驱动器及分配 2:1 1.8V PCIe Gen1-2-3 Clock Mux
* LP-HCSL outputs w/integrated terminations; saves 2 resistors compared to standard HCSL outputs * 1.8 V operation; 12 mW typical power consumption * Selectable asynchronous or glitch-free switching; allows the mux to be selected at power up even if both inputs are not running, then transition to glitch-free switching mode * Spread spectrum compatible; supports EMI reduction * OE# pins; support DIF power management * HCSL differential inputs; can be driven by common clock sources * 1 MHz to 200 MHz operating frequency * Space-saving 3x3 mm 16-pin VFQFPN; minimal board space