74HC191D

NXP  74HC191D  芯片, 74HC CMOS逻辑器件

The is a presettable synchronous 4-bit binary Up/Down Counter, pin compatible with low power Schottky TTL LSTTL. It is asynchronously presettable 4-bit binary up/down counters. They contain four master/slave flip-flops with internal gating and steering logic to provide asynchronous preset and synchronous count-up and count-down operation. Asynchronous parallel load capability permits the counter to be preset to any desired number. Information present on the parallel data inputs D0 to D3 is loaded into the counter and appears on the outputs when the parallel load PL\\ input is low. Counting is inhibited by a HIGH level on the count enable CE\\ input. When CE\ is low internal state changes are initiated synchronously by the low-to-high transition of the clock input. The up/down U\/D input signal determines the direction of counting. The CE input may go low when the clock is in either state, however, the low-to-high CE\ transition must occur only when the clock is high.

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Synchronous reversible counting

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Count enable control for synchronous expansion

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Single up/down control input

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Standard Output capability

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ICC Category