CD74HC112E

TEXAS INSTRUMENTS  CD74HC112E  触发器, 设置和复位, 互补输出, 负沿, JK, 14 ns, 60 MHz, 5.2 mA, DIP, 16 引脚

The is a dual negative-edge-triggered J-K Flip-flop with set and reset. It utilizes silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. This flip-flop has independent J, K, Set, Reset and clock inputs and Q and Q\ outputs. It changes state on the negative-going transition of the clock pulse. Set and Reset are accomplished asynchronously by low-level inputs. The HCT logic family is functionally as well as pin-compatible with the standard LS logic family.

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Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times

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Asynchronous set and reset

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Complementary outputs

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Balanced propagation delay and transition times

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Significant power reduction compared to LSTTL logic ICs

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High noise immunity

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Direct LSTTL input logic compatibility

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CMOS Input compatibility

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10 LSTTL Load standard outputs

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15 LSTTL Load bus driver outputs