KSZ8081RNACA TR

MICREL SEMICONDUCTOR  KSZ8081RNACA TR  以太网控制器, 100 Mbps, IEEE 802.3, 3.135 V, 3.465 V, QFN, 24 引脚

The is a single-supply 10Base-T/100Base-TX Ethernet Physical-layer Transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair UTP cable. This is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using on chip termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core and by offering 1.8/2.5/3.3V digital I/O interface support. It offers the reduced media independent interface RMII for direct connection to RMII-compliant MACs in Ethernet processors and switches. As the power-up default, this uses a 25MHz crystal to generate all required clocks, including the 50MHz RMII reference clock output for the MAC. This version takes in the 50MHz RMII reference clock as the power-up default.

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RMII back-to-back mode support for a 100Mbps copper repeater

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MDC/MDIO management interface for PHY register configuration

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Programmable interrupt output

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LED outputs for link and activity status indication

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On-chip termination resistors for differential pairs

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Baseline wander correction

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Auto-negotiation to automatically select highest linkup speed 10/100Mbps/duplex half/full

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Power-down and power-saving modes

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LinkMD TDR-based cable diagnostics to identify faulty copper cabling

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Parametric NAND tree support for fault detection between chip I/Os and board