74HCT273N

触发器, D, 16 ns, 36 MHz, 4 mA, DIP, 20 引脚

The is an octal positive-edge triggered D-type Flip-flop features clock and master reset MR\\ inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the low-to-high clock transition. A low on MR\ forces the outputs low independently of clock and data inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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Common clock and master reset

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TTL Input levels

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Complies with JEDEC standard No. 7A