CD74AC112EE4

双JK负边沿触发触发器具有清零和预设 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

description/ordering information

The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset PRE or clear CLR inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive high, data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse CLK.

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage

Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption

Balanced Propagation Delays

±24-mA Output Drive Current

   – Fanout to 15 F Devices

SCR-Latchup-Resistant CMOS Process and Circuit Design

Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015